In modern communications circuitry, phase-locked loops (PLL's) are used to generate output signals having arbitrary frequency by phase locking to a reference signal having a known frequency. PLL's may be implemented using analog components, a mix of analog and digital components, or they may be all-digital (e.g., ADPLL's).
The performance of PLL's can often degrade due to the coupling of spurs or other repetitive signals into the PLL. Such spurs may arise from, e.g., external sources such as power supply or RF noise, and/or internal sources such as spurs arising from integer and fractional type quantization in an ADPLL. In multi-mode phones and/or other highly integrated chip solutions, multiple systems running concurrently may exacerbate the effects of spurs on a PLL.
It would be desirable to provide techniques to improve PLL spurious performance in a wide variety of scenarios.